Computer Architecture: A Quantitative Approach, Third Edition...

Features

• Cover Type: Hard Cover with 1136 pages
• Published by: Morgan Kaufmann
• Edition: 3rd Edition May 15, 2002
• Written in: English
• ISBN 10 Number: 1558605967
• ISBN 13 Number: 978-1558605961
• Book Dimensions: 9.5 x 7.8 x 2.2 inches
• Weighs: 4.6 pounds

Book Description



This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing.



The book retains its highly rated features: Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others. In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together.



The authors present a new organization of the material as well, reducing the overlap with their other text, Computer Organization and Design: A Hardware/Software Approach 2/e, and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies.



Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. In addition to several online appendixes, two new appendixes will be printed in the book: one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom.



Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance.

* Presents state-of-the-art design examples including:
* IA-64 architecture and its first implementation, the Itanium
* Pipeline designs for Pentium III and Pentium IV
* The cluster that runs the Google search engine
* EMC storage systems and their performance
* Sony Playstation 2
* Infiniband, a new storage area and system area network
* SunFire 6800 multiprocessor server and its processor the UltraSPARC III
* Trimedia TM32 media processor and the Transmeta Crusoe processor

* looks at quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market.
Updates all the examples and figures with the most recent benchmarks, such as SPEC 2000.
* Expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors.
* Analyzes capacity, cost, and performance of disks over two decades.
Surveys the role of clusters in scientific computing and commercial computing.
* Presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems.
* Presents detailed descriptions of the design of storage systems and of clusters.
* Surveys memory hierarchies in modern microprocessors and the key parameters of modern disks.
* Presents a glossary of networking terms.

Book Info
Presents computer architecture and design as something quantitative that can be studied in the context of real running systems rather than in an abstract format. Shows the practicing engineer how technology changes over time and offers the empirical constants needed for design. Previous edition c1996.

Reader Reviews
First, this is certainly not an introductory text on Computer Architectures. The authors assume that people reading it have already had an introductory class or some experience. Simply put, the book is not intended to explain how cache memory works, but to present a thourough quantitative analysis to show why and when one implementation works better than another, and what improvements have been devised recently to speed this or this other measurement. Of course, the best choice for this book would be to have it preceeded by "Computer Organization: the HW/SW interface" (aka CO-HSI), by the same authors, since it would help to better comprehend the MIPS64 and the low-level design behind it, since CO-HSI develop an older version of the MIPS itself. This is for sure one of the most informative books I've ever encountered both as a student and as a SW engineer. It contains an overwhelming quantity of data, tips, warnings, tecniques so that the over 1100 pages seem incredibly dense. And don't be fooled the book is "only so little": there are other seven online appendixes that can be downloaded, that will add up to more than 250 pages to the book. As experience teaches, however, quantity does not always mean quality. Yet, it seems this doesn't apply to this book, because the quality of its content is highly informative and interesting for those involved with true CA designs. Since the first chapter it's clear that target of the book is not a survery of CAs, but a guide through the bunch of considerations and problems a design of a new CA must cope with today. I mean today because much of the data collected and presented is binded to (and updated to) the current edition and its realease date. So covered CAs for this 3ed will feature IA-64 or Sony Playstation II among the others. Nonetheless, it would be misleading to think that next year the book will become useless. Most of the considerations the authors develop and present are quite long lasting (the usage patterns of ISAs, e.g., have incurred little change since the second edition, six years ago). This edition presents noticeable changes, even if there's no doubt the core is that of CA-AQA 2ed. To mention a few, the first chapter is of course almost totally new since it's the most time-bounded of the book. The elder chapter four (Advanced Pipelining and Instruction Level Parallellism) has been expanded into two chapters, one dealing with Hardware approaches and one with Software approaches (and both with hybrid ones). This goes into great benefit for the reader since it seems we never get enough details on modern CAs and their complexity otherwise. However, changes has been done even in the way of reductions, and that's especially true for the elder chapter three (Pipelining). It was a full 100 pages chapter, featuring an astonishing treatment of the topic, that has been fundamental in my class of CA II. In the 3ed edition, this chapter has been moved to a shorter appendix at the end, and I think this appendix can't compare with its predecessor (even if some of the "cut" topics have been then spread through chapters 3-4 in the 3ed). About the exposition of the topics, the authors have built a solid way to make things clear for students and not, beginners and not on quantitative analysis. The book is full of figures, graph, citation and feature a wide bibliography at the end of the book and a reasoned set of references at the end of each chapter. The only difficulties reading this book will arise only because of the complexity of the topics, who themselves require a fair amount of attention, not because of the language which keeps always clear and straightforward. This said, I think the book is a fully deserved 5 stars one, with no concurrents on its kind, scope and utility. That's probabily why it has been worlwide used since its first edition. Comment | | (Report this)